library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MULTIPLY_2x8 is port(
	DINA : in  std_logic_vector(1 downto 0);
	DINB : in  std_logic_vector(7 downto 0);
	DOUT : out std_logic_vector(9 downto 0));
end MULTIPLY_2x8;

architecture RTL of MULTIPLY_2x8 is

signal RES0 : std_logic_vector(9 downto 0);
signal RES1 : std_logic_vector(9 downto 0);

begin
DOUT <= RES0 when DINA(0)= '0' else RES1;
RES0 <= ('0' & DINB & '0') when DINA(1) = '1' else "0000000000";
RES1 <= ("00" & DINB) when DINA(1) = '0' else ('0' & DINB & '0') + ("00" & DINB);
end RTL;